Company:
Tech Providers Inc.
Location: Burlingame
Closing Date: 19/11/2024
Hours: Full Time
Type: Permanent
Job Requirements / Description
Hardware Engineer/Design Verification Engineer
12+ Months Contract
Burlingame, CA (Remote)
Note: 5-15 years of relevant experience.
Mandatory Skills:
5+ years of proven experience as a DV engineer
Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Experience with UPF based simulation flow
2+ Years of experience with C/C++
Tcl and Python (or similar) scripting language
Duties:
Understanding of Ethernet / project specifications.
Writing Test plan and coverage plan.
Write testcases/scenarios.
Update existing testbench components like generators, drivers, and monitors.
Debug existing tests failing in the regression.
Work on Subsystem and system level verification.
Nice to Have:
Power and performance FPGA validation
Python scripting.
Experience with Power Aware GLS flow
ASIC design experience
Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
Experience with complex SoCs
Knowledge of coverage merging across simulation and formal
12+ Months Contract
Burlingame, CA (Remote)
Note: 5-15 years of relevant experience.
Mandatory Skills:
5+ years of proven experience as a DV engineer
Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Experience with UPF based simulation flow
2+ Years of experience with C/C++
Tcl and Python (or similar) scripting language
Duties:
Understanding of Ethernet / project specifications.
Writing Test plan and coverage plan.
Write testcases/scenarios.
Update existing testbench components like generators, drivers, and monitors.
Debug existing tests failing in the regression.
Work on Subsystem and system level verification.
Nice to Have:
Power and performance FPGA validation
Python scripting.
Experience with Power Aware GLS flow
ASIC design experience
Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
Experience with complex SoCs
Knowledge of coverage merging across simulation and formal
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